Generating Code Automatically
Verilog
 
The Verilog grammar is only available for Logic Synthesis problems and GeneXproTools 4.0 uses the basic Boolean All Gates Verilog grammar to generate Verilog code from its native Karva code.

You can translate not only all the evolved models but also exogenous models introduced through the Change Seed window into Verilog. The code can then be copied to the clipboard or saved to disk. This code can be freely distributed in source or binary form.

To translate your logic circuits into Verilog, on the GeneXproTools modeling environment, select the Model Panel, and then select both Verilog and All Gates on the Language list boxes.


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